1. Technical Field
The present invention relates generally to a semiconductor memory apparatus and to a circuit for generating a voltage in a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus operates by being applied with a voltage from an outside. In detail, a semiconductor memory apparatus is applied with an external voltage from an outside, internally generates an internal voltage, and operates using the external voltage and the internal voltage.
FIG. 1 is a diagram showing a transistor used in a cell array region, among transistors constituting a semiconductor memory apparatus.
The transistor illustrated in FIG. 1 has a gate which with a control signal CTRL, a drain which is applied with a pumping voltage VPP and a source which is applied with a ground voltage VSS, and is applied with a negative voltage VBB as a back bias voltage. The pumping voltage VPP and the negative voltage VBB are internal voltages which are generated in the semiconductor memory apparatus.
The pumping voltage VPP has a target level of a positive voltage level, and the negative voltage VBB has a target level of a negative voltage level. Therefore, after an external voltage is initially applied to the semiconductor memory apparatus, the voltage level of the pumping voltage VPP is raised to the target level of the positive voltage level, and the voltage level of the negative voltage VBB is lowered to the target level of the negative voltage level.
In the quest for the pumping voltage VPP and the negative voltage VBB to initially reach the target levels, due to a coupling characteristic between the drain and a back bias terminal, a level rise of the pumping voltage VPP applied to the drain of the transistor impedes the negative voltage VBB applied to the back bias terminal of the transistor from reaching its target level.
If the level of the pumping voltage VPP applied to the drain is raised in the situation where the negative voltage VBB used as the back bias voltage of the transistor does not reach its target level, leakage current flows between the drain and the source of the transistor.
As a consequence, in the transistor illustrated in FIG. 1, which is generally used in the cell array region, leakage current flows due to the pumping voltage VPP and the negative voltage VBB not having reached their target levels, which serves as a factor that increases current consumption of the semiconductor memory apparatus.